BH GSO IEC 60796-1:2016
IEC 60796-1:1990
								
									
									Bahraini Standard
								
								
								
									 
									Current Edition
									
								
								
									·
									Approved on
									10 February 2016
								
							
							Microprocessor system bus - 8-bit and 16-bit data (MULTIBUS I) - Part 1: Functional description with electrical and timing specifications
BH GSO IEC 60796-1:2016 Files
													English
													
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										BH GSO IEC 60796-1:2016 Scope
									This standard is applicable to interface system components, for use in interconnecting data processing, data storage, and peripheral control devices in a closely coupled configuration. This interface system contains the necessary signals to allow the various system components to interact with each other. It allows memory and Input/Output (I/O) data transfers, direct memory accesses, generation of interrupts, etc. This standard provides a detailed description of all
the elements and features that make up the system bus.
The bus supports two independent address spaces: memory and I/O.During memory cycles the bus allows direct addressability of up to 16 megabytes using 24-bit addressing. During I/O bus cycles, the bus allows addressing of up to 64K I/O ports using 16-bit addressing.Both memory and I/O cycles can support 8-bit data transfers.
The bus structure is built upon the master-slave concept where the master device in the system takes control of the bus and the slave device, upon decoding its address, acts upon the command provided by the master. This handshake (master-slave relationship) between the master and slave devices allows modules of different speeds to be
interfaced via the bus. It also allows data rates up to five million transfers per second (bytes or words) to take place across the bus.
Another important feature of the bus is the ability to connect multiple master modules for multiprocessing configurations. The bus provides control signals for connecting multiple masters in either a serial or parallel priority fashion. With either of these two arrangements,more than one master may share bus resources.
This standard has been prepared for those. users who intend to evaluate or design products that will be compatible with the system bus structure. To this end, the necessary signal definitions and timing and electrical specifications have been covered in detail.
This standard deals only with the interface characteristics of microcomputer devices and not with design specifications, performance requirements, and safety requirements of modules.
Throughout this standard, the term "system" denotes the byte or word interface system that, in general, includes all the circuits,connectors, and control protocol to effect unambiguous data transfer between devices. The term "device" or "module" denotes any product connected to the interface system that communicates information via the bus, and that conforms to the interface system definition.
									
								
							
						
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